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SRAM
Austin Semiconductor, Inc. 128K x 32 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY SPECIFICATIONS
* MIL-STD-883
AS8SLC128K32
PIN ASSIGNMENT (Top View)
68 Lead CQFP (Q)
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
FEATURES
* * * * * *
Fast Access Times of 10 to 25ns Overall Configuration: 128K x 32 4 Low Power CMOS 128K x 8 SRAMs in one MCM +3.3V power supply Internal Decoupling Capacitors Low Operating Power, 1/2 Previous Generation
OPTIONS
* Operating Temperature Ranges Military (-55oC to +125oC) Industrial (-40oC to +85oC) * Timing 10ns (Contact Factory) 12ns 15ns 17ns 20ns 25ns * Package Ceramic Quad Flatpack Pin Grid Array * Low Power Data Retention Mode
MARKINGS
XT IT
-10 -12 -15 -17 -20 -25
CS
CS2\
Vcc A11 A12 A13 A14 A15 A16 CS1\ OE\ CS2\ NC WE2\ WE3\ WE4\ NC NC NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
NC A0 A1 A2 A3 A4 A5 CS3\ GND CS4\ WE1\ A6 A7 A8 A9 A10 Vcc
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31
66 Lead PGA (P)
\
CS CS4\
\
\
NC
Q P L
\ NC
CS CS1\ CS CS3\
\
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS8SLC128K32 is a high speed, 4MB CMOS SRAM multichip module (MCM) designed for full temperature range, 3.3V power supply, military, space, or high reliability mass memory and fast cache applications. The device input and output TTL compatible. Writing is executed when the write enable (WE\) and chip enable (CS\) inputs are low. Reading is accomplished when WE\ is high and CS\ and output enable (OE\) are both low. Access time grades of 10ns, 12ns, 15ns, 17ns, 20ns and 25ns maximum are standard. The products are designed for operation over the temperature range of -55C to +125C and screened under the full military environment.
FUNCTIONAL BLOCK DIAGRAM
For more products and information please visit our web site at www.austinsemiconductor.com
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage of Vcc Supply Relative to Vss...........-0.5V to +4.6V Storage Temperature.....................................-65C to +150C Short Circuit Output Current(per I/O)............................20mA Voltage on Any Pin Relative to Vss............-.5V to Vcc+4.6V Maximum Junction Temperature**.............................+150C *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
AS8SLC128K32
This is a stress rating only and functional operation on the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See the Application Information section at the end of this datasheet for more information.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55oC < TA < 125oC and -40oC to +85oC; Vcc = 3.3V 0.3V)
DESCRIPTION Input High (logic 1) Voltage Input Low (logic 1) Voltage Input Leakage CurrentADD,OE Input Leakage CurrentWE,CE Output Leakage CurrentI/O Output High Voltage Output Low Voltage 0VCONDITIONS SYMBOL
CONDITIONS
SYMBOL VIH VIL ILI1 ILI2 ILO VOH VOL
-10 280 -12 240
MIN 2.2 -0.3 -10 -10 -10 2.4
MAX VCC+0.3 0.8 10 10 10
UNITS NOTES V V A A A V 1 1 1 1
0.5
MAX -15 220
V
DESCRIPTION
-17 180
-20 160
UNITS NOTES
CS\VIH; VCC = MAX Power Supply Current: Standby f = MAX = 1/ tRC (MIN) Outputs Open, OE\=VIH Low Power (L) VIN = VCC - 0.2V, or VSS +0.2V VCC=Max; f = 0Hz Low Power (L)
AS8SLC128K32 Rev. 0.6 06/05
ICC1
mA
2, 3,13
240 --80
210 --60
200 --60
180 --60
160 --60
ICC3
mA
2
ISBT1
100 80 70 50
2
80 60 60 36
80 60 60 36
80 60 60 36
80 60 60 36
mA
3, 13
CMOS Standby
ISBT2
mA
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SRAM
Austin Semiconductor, Inc.
CAPACITANCE (VIN = 0V, f = 1MHz, TA = 25oC)*
SYMBOL CADD COE CWE, CCS CIO PARAMETER A0 - A16 Capacitance OE\ Capacitance WEx\ and CSx\ Capacitance I/O 0- I/O 31 Capacitance MAX 40 40 12 15 UNITS pF pF pF pF
AS8SLC128K32
NOTE: *This parameter is sampled.
AC TEST CONDITIONS
TEST SPECIFICATIONS
Input pulse levels...........................................VSS to 3V Input rise and fall times...........................................1ns/V Input timing reference levels...............................1.5V Output reference levels........................................1.5V Output load..........................................See Figure 1, 2
3.3V RL = 50 Q ZO = 50 30 pF VL = 1.5V Q 333 5 pF 319
FIGURE 1
FIGURE 2
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
Austin Semiconductor, Inc.
AS8SLC128K32
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTE 5) (-55oCDESCRIPTION
READ CYCLE READ cycle time Address access time Chip select access time Output hold from address change Chip select to output in Low-Z Chip select to output in High-Z Output enable access time Output enable to output in Low-Z Output disable to output in High-Z WRITE CYCLE WRITE cycle time Chip select to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width, CS\ controlled WRITE pulse width, WE\ controlled Data setup time Data hold time Write disable to output in Low-z Write enable to output in High-Z
SYMBOL
RC AA t ACS t OH t LZCS t HZCS t AOE t LZOE t HZOE
t t
-10 MIN MAX
10 10 10 1 1 0 0 5.5 5.5 5.5 10 9 9 0 0 9 9 5 1 2 5
-12 MIN MAX
12 12 12 2 2 0 0 6 6 6 12 10 10 0 0 10 10 6 1 2 5
-15 MIN MAX
15 15 15 2 2 0 0 7 7
-17 MIN MAX
17 17 17 2 2 7.5 7.5 0 7.5 17 11 11 0 0 14 14 7.5 1 2 6.5
-20 UNITS NOTES MIN MAX
20 20 20 2 2 0 0 8 8 8 20 12 12 0 0 15 15 8 1 2 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4,6,7 4,6,7 4,6 4,6
7 15 10 10 0 0 12 12 7 1 2 6
WC CW t AW t AS t AH t WP1 t WP2 t DS t DH t LZWE t HZWE
t
t
4,6,7 4,6,7
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
Austin Semiconductor, Inc.
LOW POWER CHARACTERISTICS (L Version Only)
DESCRIPTION VCC for Retention Data Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CONDITIONS All Inputs @ Vcc + 0.2V or Vss + 0.2V, CS\ = Vcc + 0.2V VCC = 2V VCC = 3V SYMBOL VDR ICCDR ICCDR tCDR tR 0 20 MIN 2 MAX 24 32 UNITS V mA mA ns ms 4 4, 11 NOTES
AS8SLC128K32
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
4.5V VDR > 2V
t
4.5V
CDR
t
R
CS\ 1-4
VDR
NOTES
1. All voltages referenced to VSS (GND). 2. Worst case address switching. 3. ICC is dependent on output loading and cycle rates. unloaded, and f= 1 t RC(MIN) HZ. tHZCS, is less than tLZCS, and tHZWE is less than tLZWE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip selects and output enable are held in their active state. 10. Address valid prior to or coincident with latest occurring chip enable. 11. tRC= READ cycle time. 12. Chip enable (CS\) and write enable (WE\) can initiate and terminate a WRITE cycle. 13. ICC is for full 32 bit mode.
The specified value applies with the outputs 4. This parameter guaranteed but not tested. 5. Test conditions as specified with output loading as shown in Fig. 1 & 2 unless otherwise noted. 6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in Fig. 2. Transition is measured +/- 200 mV typical from steady state voltage, allowing for actual tester RC time constant. 7. At any given temperature and voltage condition,
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
765432 74341 5432 76543210987654321 56523210987654321 1 74341 56523210987654321 7 76543 5434121 7432121 56523210987654321 74343 56543 10987654321 4341 76523210987654321 56521210987654321 76543 54321210987654321 7654321
76543210987654321 7654321 54321 76543210987654321 76543210987654321 1 76543210987654321 7654321 5432 76543210987654321 765432 76543210987654321 54321 76543210987654321 1 76543210987654321
ADDRESS
Austin Semiconductor, Inc.
READ CYCLE NO. 1
tOH
54326 651 1 7 4 7154321321 5432154321321 16 654 4 5432154321321 1 76 651 5432154321321 16 654 7
ADDRESS
DATA I/O
PREVIOUS DATA VALID
READ CYCLE NO. 2
tAA
tAA
987 665432654321 7 987 7654326 6543211 654326 754321154321 654321154321 987 7654326 654321154321 987
876543211 5321 432 876544321 5432 54321 876554321 4321 876543211
CS\
t tLZCS ACS
665430 7 21 7543229 654321187654321 654329 210 0 7654329 665431187654321 212 754321187654321 654321187654321 210 7654329 654321187654321 2109
tHZCS
2109876544321 5321 432 432 53211 2109876543211 2109876544321 5432 432 54321 2109876554321 43211 2109876543211
OE\
tAOE tLZOE
5432341 15 3 4 543212121 15 3 45 3 543212121 13 3 414121 543212121 1541 4341 543212121 1323 434 5
AS8SLC128K32 Rev. 0.6 06/05
DATA I/O
HIGH IMPEDANCE
6 tRC tRC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
NEW DATA VALID
DATA VALID
tHZOE
AS8SLC128K32
SRAM
ADDRESS
Austin Semiconductor, Inc.
CS\
WRITE CYCLE NO. 1
tAS
(Chip Select Controlled)
t AW
tCW
t WP2 1
6 5532 643220 543211987654321 54320 431 654320 554311987654321 2 643211987654321 543211987654321 3210 654320 543211987654321
tAH
87654321 87654321 87654321 87654321 87654321 654321 654321 654321 654321
DATA I/O
ADDRESS
WE\
WRITE CYCLE NO. 2
(Write Enable Controlled)
t AW
tCW
7543211987654321 654320987654321 321 7543211987654321 654320 7543211987654321 654321 321 7543210 654320
tAH
87654321 5432 876543211 54321 432 876543211 54321 4321 876543211 5432
CS\
tAS
654321 654321 654321 654321 654321
WE\
tHZWE
t WP1 1
tWC
tWC
DATA VALID
tDS
tDS
tLZWE tDH
43211 432 4321 43211 432 4321 43211 432
43113210987654321 24 5 43513210987654321 14 2 1 43113210987654321 24 5 1
AS8SLC128K32 Rev. 0.6 06/05
1. All voltages referenced to VSS (GND).
NOTES
DATA I/O
7
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
DATA VALID
tDH
AS8SLC128K32
SRAM
SRAM
Austin Semiconductor, Inc.
AS8SLC128K32
MECHANICAL DEFINITIONS*
ASI Case (Package Designator Q)
D2 D1 D
DETAIL A
R
1o - 7o b L1
B
e SEE DETAIL A
A A2 E3
SMD SPECIFICATIONS SYMBOL A A1 A2 B b D D1 D2 E e R L1 MIN 0.123 0.118 0.005 0.010 REF 0.013 0.800 BSC 0.870 0.980 0.936 0.050 BSC 0.010 TYP 0.035 0.045 0.890 1.000 0.956 0.017 MAX 0.200 0.186 0.015
*All measurements are in inches.
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
Austin Semiconductor, Inc.
AS8SLC128K32
MECHANICAL DEFINITIONS*
ASI Case (Package Designator P)
4xD D1 Pin 56 D2 Pin 1
(identified by 0.060 square pad)
A A1
b1
E1
e
b
Pin 66 e b2 Pin 11 L
SMD SPECIFICATIONS SYMBOL A A1 b b1 b2 D D1/E1 D2 e L MIN 0.135 0.025 0.016 0.045 0.065 1.064 1.000 BSC 0.600 BSC 0.100 BSC 0.145 0.155 MAX 0.195 0.035 0.020 0.055 0.075 1.086
*All measurements are in inches.
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
SRAM
Austin Semiconductor, Inc.
AS8SLC128K32
ORDERING INFORMATION
EXAMPLE: AS8SLC128K32Q-20/883C Device Number AS8SLC128K32 AS8SLC128K32 AS8SLC128K32 AS8SLC128K32 AS8SLC128K32 Package Type Q Q Q Q Q Speed ns -20 -25 -35 -45 -55 Options Process L L L L L /* /* /* /* /*
EXAMPLE: AS8SLC128K32P-35L/IT Device Number AS8SLC128K32 AS8SLC128K32 AS8SLC128K32 AS8SLC128K32 AS8SLC128K32 Package Type P P P P P Speed ns -20 -25 -35 -45 -55 Options Process L L L L L /* /* /* /* /*
*AVAILABLE PROCESSES
XT = Military Temperature Rang IT = Industrial Temperature Range 883C = Full Military Processing -55oC to +125oC -40oC to +85oC -55oC to +125oC
OPTION DEFINITIONS
L = 2V data retention/low power
AS8SLC128K32 Rev. 0.6 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10

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